View IRMCK099M-15_8955261.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

irmck099m 1 www.irf.com ? 20 14 international rectifier d ecember 18 , 2014 high performance sensorless motor control ic description irmck099 is a low cost, high performance otp memory based motion control as ic designed primarily for appliance applications. irmck099 is designed to implement high performance control solutions fo r advanced inverterized appliance motor control. irmck099 contains the f lexible tiny motion control engine ( tiny mce) for sensorless control of permanent magnet motors over the full speed range . the tinymce implements sensorless field oriented control using single or leg shunt current feedback by a combination of hardware and ir - supplied firmware elements. key components of the complex sensorless control algorithms, such as the angle estimator, are provided as complete pre - defined control blocks. t he asic i s designed to eliminate external components and reduce cost by including an a/d converter, analog amplifiers, an overcurrent comparator, watchdog timer and internal oscillator. strong startup and configuration tools get the motor running quickly without an y programming. a standby power mode can help to increase overall system efficiency. irmck099 comes in a 5mmx5mm, 32 pin qfn package. features ? t iny mce ( tiny motion control engine) - dedicated computation engine for high efficiency sinusoidal sensorless motor control ? internal oscillator C no clock required ? built - in hardware peripheral for single or two shunt current feedback reconstruction and anal og circuits ? supports both interior and surface permanent magnet motor sensorless control ? loss minimization space vector pwm ? internal itrip comparator ? t wo - channel analog output ( sigma delta d/a ) ? jtag programming port for debugg ing ? uart and i2c serial interf ace ? factory calibrated analog inputs ? c apture input ? watchdog timer with independent internal clock ? standby low power mode ? internal 16 kbyte otp memory ? crc memory check ? 3.3v single supply product summary internal clock frequency (sysclk) 1 0 0mhz mce tm computa tion time 1 sysclk mce tm computation data range 16 bit signed otp memory 16 kb mce data ram 1.5 kb mce program ram 12 kb fault latency (digital filtered) 2 sec pwm carrier frequency 1 C 20khz a/d input channels 6 a/d converter resolution 12 bits a/d converter conversion speed 2 sec analog output (pwm) resolution 8 bits uart baud rate (typ) 57.6 k bps numb er of digital i/o (max) 8 package (lead free) qfn 5x5 32l typical 3.3v operating current < 30 ma standyby mode power consumption 3.5mw integrated temperature sensor (typ) 5degc base part number package type standard pack orderable part number form quant ity irmck099m qf n32 tape and reel 3 000 irmck099 m tr tray 2450 irmck099m
irmck099m 2 www.irf.com ? 20 14 international rectifier d ecem ber 1 8 , 2014 table of contents 1 overview ................................ ................................ ................................ ................................ ................................ .... 5 2 pinout ................................ ................................ ................................ ................................ ................................ ......... 6 3 irmck099 block diagr am and main function s ................................ ................................ ................................ .... 8 4 application connecti on and pin function ................................ ................................ ................................ .......... 9 4.1 mce p eripheral i nterface g roup ................................ ................................ ................................ ................................ ..... 9 4.2 m otion p eripheral i nterface g roup ................................ ................................ ................................ .............................. 10 4.3 a nalog i nterface g roup ................................ ................................ ................................ ................................ ............... 10 4.4 p ower i nterface g roup ................................ ................................ ................................ ................................ ................. 11 4.5 t est i nterface g roup ................................ ................................ ................................ ................................ .................... 11 5 dc chara cteristics ................................ ................................ ................................ ................................ .................. 12 5.1 a bsolute m aximum r atings ................................ ................................ ................................ ................................ .......... 12 5.2 s ystem c lock f requency and p ower c onsumption ................................ ................................ ................................ ......... 12 5.3 d igital i/o dc c haracteristics ................................ ................................ ................................ ................................ ...... 13 5.4 a nalog i/o dc c haracteristics ................................ ................................ ................................ ................................ ...... 14 5.5 a/d a ccuracy an d l inearity ................................ ................................ ................................ ................................ ........... 14 5.6 u nder v oltage l ockout dc characteristics ................................ ................................ ................................ ................... 15 5.7 i trip comparator dc characteristics ................................ ................................ ................................ ............................. 15 5.8 w ake - up threshold dc characteristics ................................ ................................ ................................ .......................... 15 5.9 i ntegrated t emperature s ensor ................................ ................................ ................................ ................................ .... 15 6 ac characteristics ................................ ................................ ................................ ................................ .................. 16 6.1 i nternal o scillator ac c haracteristics ................................ ................................ ................................ ......................... 16 6.2 a nalog to d igital c onverter ac c haracteristics ................................ ................................ ................................ ........... 16 6.3 o p amp ac c haracteristics ................................ ................................ ................................ ................................ ............ 17 6.4 sync to svpwm and a/d c onversion ac t iming ................................ ................................ ................................ .......... 18 6.5 fault to svpwm ac t iming ................................ ................................ ................................ ................................ ........ 19 6.6 itrip ac t iming ................................ ................................ ................................ ................................ ............................. 19 6.7 i 2 c ac t iming ................................ ................................ ................................ ................................ ................................ 20 6.8 uart ac t iming ................................ ................................ ................................ ................................ ............................ 21 6.9 capture i nput ac t iming ................................ ................................ ................................ ................................ ............. 22 6.10 jtag ac t iming ................................ ................................ ................................ ................................ ......................... 23 7 i/o structure ................................ ................................ ................................ ................................ ........................... 24 8 pin list ................................ ................................ ................................ ................................ ................................ ....... 26 9 package dimensions ................................ ................................ ................................ ................................ ............... 27 10 part marking informa tion ................................ ................................ ................................ ............................... 28 11 qualification inform ation ................................ ................................ ................................ ............................... 28
irmck099m 3 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 list of tables t able 1 r emap functions avail able on gpio ................................ ................................ ................................ ..................... 7 t able 2. a bsolute m aximum r atings ................................ ................................ ................................ ................................ .. 12 t able 3. s ystem c lock f requency and p ower c onsumption ................................ ................................ ...................... 12 t able 4. d igital i/o dc c haracteristics ................................ ................................ ................................ .......................... 13 t able 5. a nalog i/o dc c haracteristics ................................ ................................ ................................ .......................... 14 t able 6. uv cc 3.3v dc c haracteristics ................................ ................................ ................................ .......................... 15 t able 7. i trip dc c haracteristics ................................ ................................ ................................ ................................ ..... 15 t able 8. w ake - up threshold dc c haracteristics ................................ ................................ ................................ ......... 15 t able 9. i nternal o scillator ac c haracteristics ................................ ................................ ................................ ........ 16 t able 10.a/d c onverter ac c haracteristics ................................ ................................ ................................ ................ 16 t able 11 c urrent s ensing op a mp ac c haracteristics ................................ ................................ .............................. 17 t able 12. sync ac c haracteristics ................................ ................................ ................................ ................................ 18 t able 13. fault to svpwm ac t iming ................................ ................................ ................................ ............................. 19 t able 14. i tri p ac t iming ................................ ................................ ................................ ................................ ...................... 19 t able 15. i 2 c ac t iming ................................ ................................ ................................ ................................ ......................... 20 t able 16. uart ac t iming ................................ ................................ ................................ ................................ .................... 21 t able 17. capture ac t iming ................................ ................................ ................................ ................................ ........... 22 t able 18. jtag ac t iming ................................ ................................ ................................ ................................ .................... 23 t able 19. p in l ist ................................ ................................ ................................ ................................ ................................ ... 26
irmck099m 4 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 list of figures f igure 1. t ypical a pplication b lock d iagram u sing irmck099 ................................ ................................ ................... 5 f igure 2. p inout of irmck099 ................................ ................................ ................................ ................................ ............. 6 f igure 3. irmc k099 b lock d iagram ................................ ................................ ................................ ................................ .... 8 f igure 4. irmck099 l eg s hunt c onnection d iagram ................................ ................................ ................................ ..... 9 f igure 5. v oltage droop and s/h hold time ................................ ................................ ................................ .................... 16 f igure 6. o p amp output capacit or ................................ ................................ ................................ ................................ ... 17 f igure 7. sync timing ................................ ................................ ................................ ................................ ........................... 18 f igure 8. f aul t timing ................................ ................................ ................................ ................................ ........................... 19 f igure 9. itrip timing ................................ ................................ ................................ ................................ ........................... 19 f igure 10. i 2 c t iming ................................ ................................ ................................ ................................ ............................. 20 f igure 11. uart timing ................................ ................................ ................................ ................................ ......................... 21 f igure 12. capture timing ................................ ................................ ................................ ................................ ................ 22 f igure 13. jtag timing ................................ ................................ ................................ ................................ ......................... 23 f igure 14. d igital i/o s tructure ................................ ................................ ................................ ................................ ....... 24 f igure 15. a nalog i/o s tructure ................................ ................................ ................................ ................................ ...... 24 f igure 16 a nalog a nalog i nput s tructure for ain0/stby ................................ ................................ ....................... 24 f igure 17. vss pin i/o structure ................................ ................................ ................................ ................................ ....... 25 f igure 18. vddcap pin i/o structure ................................ ................................ ................................ .............................. 25 f igure 19. vdd1 pin i/o structure ................................ ................................ ................................ ................................ .... 25
irmck099m 5 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 1 overview irmck099 is a new generation international rectifier integrated circuit device primarily designed as a one - chip solution for inverter ized appliance motor control applications. unlike a traditional microcontroller or dsp, the irmck09 9 provides a built - in closed loop sensorless control algorithm using the unique flexible tiny motion control engine ( tiny mce) for permanent magnet motors. the mce tm consists of a collection of control elements, motion peripherals, a dedicated motion contr ol sequencer and internal memory to map internal signal nodes. irmck099 also employs a unique single shunt current reconstruction circuit in addition to two leg shunt current sensing circuit to eliminate additional analog/digital circuitry . integrated op - amps and a/d converter enable a direct shunt resistor interface to the ic. four analog inputs and up to eight dig ital i/o provide resources for application specific functions . figure 1 shows a typical application schematic using the irmck099 . irmck099 contains 16 kbytes of otp program memory and come s in a compact 5mm x 5mm 32 - pin qfn package. figure 1 . typical application block diagram using irmck099 i r m c k 0 9 9 p o w e r s u p p l y g a t e d r i v e p m m o t o r i p m o r s p m p a s s i v e e m i f i l l t e r d i g i t a l i / o a n a l o g i n p u t h o s t c o m m u n i c a t i o n ( r s 2 3 2 c ) a p p l i a n c e p m m o t o r d r i v e 3 . 3 v g a t e s i g n a l 1 5 v e e p r o m 5 2 8 g a l v a n i c i s o l a t i o n o p t i o n a l
irmck099m 6 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 2 pinout figure 2 . pinout of irmck099 3 4 5 6 7 8 2 1 a i n 0 / v s p t d o / g p i o 1 4 / g p i o 1 5 g p i o 7 a i n 1 / v b u s a i n 2 i f b 2 o t d i / g p i o 1 4 / g p i o 1 5 t c k a i n 3 g p i o 1 1 g p i o 1 0 g p i o 9 g p i o 2 g p i o 0 g p i o 1 3 v d d 1 v d d c a p i f b 1 + g p i o 3 g p i o 6 g p i o 5 i r m c k 0 9 9 ( t o p v i e w ) i f b 1 o v p p t m s / g p i o 1 4 g p i o 4 i f b 1 - i f b 2 + i f b 2 - g p i o 8 g p i o 1 2 1 3 1 4 1 5 1 6 1 1 1 0 1 2 9 1 8 1 9 2 0 2 1 2 2 2 3 2 4 1 7 2 5 2 6 3 2 3 1 3 0 2 9 2 8 2 7 g p i o 1 v s s
irmck099m 7 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 pin number pin name main function (after reset) (1) remap (1) ( 2 ) 1 tdi/gpio14/gpio15 tdi g atekill pwmul pwmuh pwmvl pwmvh pwmwl pwmwh aopwm0 aopwm1 rxd txd sda scl capture 3 tms/gpio14 tms 18 gpio8 (1) 19 gpio9 20 gpio10 21 gpio11 22 gpio12 23 gpio13 24 gpio0 25 gpio1 26 gpio2 27 gpio3 28 gpio4 29 gpio5 30 gpio6 31 gpio7 32 tdo/gpio14/gpio15 tdo table 1 remap functions available on gpio note (1) - function availability depends on the provided firmware and for more information refer to the application pin out section of the irmck099 application guide. note (2) - only one pin can be remapped to one of the provided functions at the same time, for more in formation refer to the application pin out section of the irmck099 application guide.
irmck099m 8 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 3 irmck099 block diagram and main functions irmck099 block diagram for leg shunt mode is shown in figure 3 . figure 3 . irmck099 block diagram irmck099 contains the following functions for sensorless permanent magnet motor control applications: tiny motion control engine ( tiny mce) ? sensorless foc (complete sensorless field oriented control) o pi speed regulator o 2 - channel pi current regulators (q & d quadratures) o angle estimat or (sensorless control) o clark/ inverse clark transformation o vector rotator o no parking o torque at low to zero speed o multiply - divide (signed and unsigned) o divide (si gned and unsigned) o atan (arc tangent) ? hardware pwm shutdown pin ( gk ) ? up to 20khz pwm frequency ? one 16 bit watchdog timer ? one 16 bit capture timer ? up to 8 discrete digital i/os ? six - channel 12 bit a/d o buffered (current sensing) two channels (0 C 1.2 v input) o unbuffered four channels (0 C 1.2 v input) ? jtag port (4 pins) ? two channels analog output (8 bit pwm) ? uart ? i 2 c port ? standby low power mode ? 1.5 k byte data ram ? 12k byte p rogram ram ? 16 k byte otp memory m o t i o n c o n t r o l s e q u e n c e r m o t i o n h a r d w a r e a c c e l e r a t o r s m c e p r o g r a m r a m 6 k b y t e o t p m e m o r y 1 6 - b i t m o t i o n c o n t r o l b u s a n a l o g i n t e r f a c e d / a w a t c h d o g t i m e r u a r t i 2 c m o t i o n p e r i p h e r a l s o v e r c u r r e n t p r o t e c t i o n t o g a t e d r i v e t i n y m o t i o n c o n t r o l e n g i n e ( t i n y m c e ) j t a g e m u l a t o r d e b u g g e r 4 1 0 0 m h z i n t e r n a l o s c i l l a t o r a n a l o g i n p u t c a p t u r e f r o m s h u n t r e s i s t o r ( s ) g p i o p o r t s s c l s d a a / d c o n v e r t e r r x d t x d a o p w m 0 a o p w m 1 c a p p w m o u t p u t s 8 g a t e k i l l d a t a r a m 1 . 5 k b y t e 6 i f b 1 3 i f b 2 3 a i n 0 / v s p a i n 1 / v b u s a i n 2 a i n 3 t e m p e r a t u r e s e n s i n g
irmck099m 9 www.irf.com ? 20 14 international rectifier d ecem ber 1 8 , 2014 4 application connection and pin function figure 4 shows the application connections in leg shunt mode. figure 4 . irmck099 leg shunt connection diagram 4.1 mce peripheral interface group uart interfa ce txd output, transmit data from irmck099 , can be configured to gpio pins rxd input, receive data to irmck099 , can be configured to gpio pins discrete i/o interface gpio0 - gpio15 digital input/output ports t x d r x d p w m u h p w m u l p w m v h p w m v l p w m w h p w m w l g a t e k i l l a i n 0 h o s t m i c r o c o n t r o l l e r ( r s 2 3 2 c ) d i g i t a l i / o c o n t r o l a n a l o g o u t p u t t d i j t a g c o n t r o l ( o t p p r o g r a m m i n g & e m u l a t i o n ) t c l k t m s t d o a v r e f i f b 1 + i f b 1 - i f b 1 o 1 . 8 v v d d 1 3 . 3 v v s s i f b 0 + i f b 0 - i f b v 0 i n t e r n a l o s c i l l a t o r r s 2 3 2 c g p i o p o r t r e s e t p w m 0 j t a g i n t e r f a c e l o w l o s s s p a c e v e c t o r p w m s / h s / h f o c b l o c k m o t i o n c o n t r o l s e q u e n c e r 1 2 b i t a / d & m u x s y s t e m c l o c k m c e m e m o r y ( 1 2 k b y t e ) d a t a r a m ( 1 . 5 k b y t e ) s y s t e m r e s e t w a t c h d o g t i m e r i r m c k 0 9 9 v p p 1 . 8 v v o l t a g e r e g u l a t o r v d d c a p 3 . 3 v o t p p r o g r a m m i n g v o l t a g e ( 6 . 5 v ) m o t o r i r h i g h v o l t a g e g a t e d r i v e i c + 1 . 8 v c u r r e n t s e n s i n g l o g i c a o p w m 0 g p i o 4 g p i o 3 g p i o 2 f a u l t d e t e c t i o n a n g l e e s t i m a t o r o t p m e m o r y ( 1 6 k b y t e ) g p i o 6 g p i o 5 g p i o 7 a o p w m 1 p w m 1 s e r i a l e e p r o m ( i 2 c ) s d a s c l i 2 c t e m p e r a t u r e s e n s i n g a n a l o g / d i g i t a l c o r e v o l t a g e a i n 1 a i n 2 a i n 3 0 . 3 v e n a b l e / d i s a b l e s t a n d b y m o d e u n d e r v o l t a g e l o c k o u t 3 . 3 v g p i o 1 g p i o 8
irmck099m 10 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 analog output interface aopwm1 input/output, can be configured as 8 - bit pwm output 1 with programmable carrier frequency aopwm2 input/output, can be configured as 8 - bit pwm output 2 with programmable carrier frequency i 2 c interface scl output, i 2 c clock output , can be configured to gpio pins sda inp ut/output, i 2 c data line , can be configured to gpio pins capture interface cap capture input , can be configured to gpio pins 4.2 motion peripheral interface group pwm pwmuh output, pwm phase u high side gate signal , tri - state at power up until configured by firmware pwmul output, pwm phase u low side gate signal, tri - state at power up until configured by firmware pwmvh output, pwm phase v high side gate signal, tri - state at power up until configured by firmware pwmvl output, pwm phase v low side gate signal, tri - state at power up until configured by firmware pwmwh output, pwm phase w high side gate signal, tri - state at power up until configured by firmware pwmwl output, pwm phase w low side gate signal, tri - state at power up until configured by firmware gatek ill gk input, upon assertion this sets all six pwm signals to off state according to setting of active_pol register , pulled up by 49kohm internal resistor 4.3 analog interface group ifb 1 + input, operational amplifier positive input for single or leg shunt res istor current sensing ifb 1 - input, operational amplifier negative input for single or leg shunt resistor current sensing ifb 1 o output, operational amplifier output for single or leg shunt resistor current sensing ifb2+ input, operational amplifier positiv e input for 2 nd leg shunt resistor current sensing ifb2 - input, operational amplifier negative input for 2 nd leg shunt resistor current sensing ifb2o output, operational amplifier output for 2 nd leg shunt resistor current sensing ain0 /vsp input, analog in put channel 0 (0 C 1.2 v), also used for standby mode wake - up ain1 /vbus input, analog input channel 1 (0 C 1.2 v), typically configured for dc bus voltage input ain2 input, analog input channel 2 (0 C 1.2 v), needs to be pulled down to vss if unused ain 3 input, analog input channel 3 (0 C 1.2 v), needs to be pulled down to vss if unused
irmck099m 11 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 4.4 power interface group vdd1 digital and analog power (3.3v) vddcap internal 1.8v output, require capacitors connected to the pin. note: the internal 1.8v supply is no t designed to power any external circuits or devices. only capacitors should be connected to this pin. vss digital and analog common 4.5 test interface group tms jtag test mode input or input digital port tdo jtag data output tdi jtag data input, or input di gital port tck jtag test clock
irmck099m 12 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 5 dc characteristics 5.1 absolute maximum ratings symbol parameter min typ max condition v dd1 supply voltage - 0.3 v - 3.6 v respect to vss v ia analog input voltage - 0.3 v - 1.98 v respect to vss v id digital input voltage - 0.3 v - 3.6 v respect to vss t a ambient temperature - 40 ?c - 125 ?c t s storage temperature - 65 ?c - 150 ?c table 2 . absolute maximum ratings caution: stresses beyond those listed in absolute maximum ratings may cause perman ent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 system clock frequency and power consumption v dd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max unit sysclk system clock - 100 - mhz p d power c onsumption 1 0 0 1) - mw p stby standby power consumption 3.5 mw table 3 . system clock frequency and power consum ption note 1) the value is based on the condition of mce clock=1 0 0mhz with a n actual motor running by a typical tiny mce application program.
irmck099m 13 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 5.3 digital i/o dc characteristics symbol parameter min typ max condition v dd1 supply voltage 3.0 v 3.3 v 3.6 v recommended v il input low voltage - - 0.8 v recommended v ih input high voltage 2.0 v - recommended c in input capacitance - 1.6 pf - (1) i l input leakage current 10 na 1 a o = 3.3 v or 0 v i ol low level output current 14.1ma 22.9ma 31.8ma v ol = 0.4 v (1) i oh high level output current 21.8ma 44.2ma 73.5ma v oh = 2.4 v (1) table 4 . digital i/o dc characteristics note: (1) data guaranteed by desig n.
irmck099m 14 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 5.4 analog i/o dc c haracteristics - op amp s for current sensing ( ifb 1 +,ifb 1 - ,ifb 1 o, ifb 2 +,ifb 2 - ,ifb 2 o ) vdd1=3.3v, unless specified, ta = 25?c. symbol parameter min typ max condition v offset input offset voltage - 20mv 3 mv 20mv v vdd1 = 3.3 v v i input voltage range 0 v 1.2 5 v recommended v outsw op amp output operating range 50 mv (1) - 1. 7 v v vdd1 = 3.3 v c in input capacitance - 3.6 pf - r fdbk op amp feedback resistor 5 k ? ? gaincl operating open loop gain - 80 db - (1) cmrr common mode rejection ratio - 80 db - (1) i src op amp output source current - 1 ma - v out = 0.6 v i snk op amp output sink current - 100 a out = 0.6 v table 5 . analog i/o dc characteristics note: (1) data guaranteed by design. 5.5 a/d accuracy and linearity unless specified, ta = 25?c. a/d accuracy for current sensing ( ifb 1 +,ifb 1 - ,ifb 1 o, ifb 2 +,ifb 2 - ,ifb 2 o ) , vdc (ain1) sensing and analog input channels (ain0,ain2, ain3) symbol parameter min typ max condition adc error error is the difference between ideal counts and compensated counts for any applied voltage in 0 - 1.2 v range 0 10counts 20counts (1) adci nl integral non linearity 4 counts (1) (2) full 12bit range adcdnl differential non linearity 1. 4 counts (1) (2) full 12bit range table 5 . a/d accuracy note: (1) characteri zation only (2) the value is based on the con dition of mce clock=100mhz with an actual motor running by a typical tinymce application program.
irmck099m 15 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 5.6 under voltage lockout dc characteristics unless specified, ta = 25?c. symbol parameter min typ max condition uv cc 3.3 + uvc c positive going threshold 2. 55 v 2.7 8 v 3.00v uv cc 3.3 - uvcc negative going threshold 2. 40 v 2.6 5 v 2. 85 v uv cc 3.3 h uvcc hysteresys - 100mv - (1) table 6 . uvcc 3.3v dc characteristics note: (1) data guaranteed by design. 5.7 itrip comp arator dc characteristics unless specified, vdd1=3.3v, ta = 25?c. symbol parameter min typ max condition itrip + itrip positive going threshold 1. 2 82 v 1.3 42 v 1.4 02 v v dd1 = 3.3 v , ta=0 - 85c (2) itrip - itrip negative going threshold 1.05v 1.1 24v 1. 25 v v dd1 = 3.3 v itriph itrip hyst eresys 0.05v 0. 218 v 0.3v (1) table 7 . itrip dc characteristics note: (1) data guaranteed by design . (2) characterization only . 5.8 wake - up threshold dc characteristics unless specified, vdd1=3.3v, ta = 25?c. symbol parameter min typ max condition v wk exit from standby threshold 0.2 85 v 0.3 15 v 0.3 45 v v dd1 = 3.3 v table 8 . wake - up threshold dc characteristics 5.9 integrated temperature sensor unless specified, vdd1=3.3v symbol parameter min typ max condition t sense integrated t sense error - 5?c dd1 = 3.3 v ta = - 40 ?c 25?c 25?c table 8 . wake - up threshold dc characteristics
irmck099m 16 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 6 ac c haracteristics 6.1 internal oscillator ac c haracteristics unless specified, ta = 25?c. vdd1 = 3.3v symbol parameter min typ max condition f clk clock frequency 9 9 mhz 100 .0 mhz 10 1 mhz 95.8mhz (1) 104.4mhz (1) ta= - 40c C note: (1) characterization only table 9 . internal oscillator ac characteristics 6.2 analog to digital converter ac c haracteristics unless specifie d, ta = 25?c. symbol parameter min typ max condition t conv conversion time - - 2.05 sec (1) t hold sample/hold maximum hold time - - 10 sec voltage droop 15 table 10 . a/d converter ac characteristics note: (1 ) data guaranteed by design. figure 5 . voltage droop and s/h hold time t h o l d v o l t a g e d r o o p t s a m p l e s / h v o l t a g e i n p u t v o l t a g e
irmck099m 17 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 6.3 op amp ac c haracteristics unless specified, ta = 25?c. symbol parameter min typ max condition op sr op amp slew rate - 10 v/sec (1) op imp op input impedance - 10 8 (1) (2) t set settling time - 400 ns - vdd1 = 3.3 v, cl = 33 pf (1) table 11 current sensing op amp ac characteristics note: (1) data guaranteed by des ign. (2) to guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 100 pf , see figure 6 . here only the single shunt current amplifier is show n but al l op amp outputs should be loaded with this capacitor value . figure 6 . op amp output capacitor a v r e f i f b + i f b - i f b o i r m c k 0 9 9 i c e x t e r n a l c o m p o n e n t s 1 0 0 p f
irmck099m 18 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 6.4 sync to svpwm and a/d conversion ac t iming figure 7 . sync timing unless specified, ta = 25?c. symbol parameter min typ max unit t wsync sync pulse width - 32 - sysclk (1) t dsync1 sync to current feedback conversion time - - 100 t dsync2 sync to ain0 - 3 - - 200 t dsync3 sync to pwm output delay time - - 2 table 12 . sync ac characteristics note: (1) characteri zation only s y n c i u , i v , i w t w s y n c t d s y n c 1 a i n x t d s y n c 2 p w m u x , p w m v x , p w m w x t d s y n c 3
irmck099m 19 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 6.5 fault to svpwm ac t iming f igure 8 . fault timing unless specified, ta = 25?c. symbol parameter min typ max unit t wgk fault pulse width 32 - - sysclk t dgk fault to pwm output delay - - 100 sysclk table 13 . fault to svpwm ac timing 6.6 itrip ac t iming figure 9 . itrip timing unless specified, ta = 25?c. symbol parameter min typ max unit t itrip itrip propagation delay - 470ns - ns (1) table 14 . itrip ac timing note: (1) characteri zation only g a t e k i l l p w m u x , p w m v x , p w m w x t w g k t d g k i t r i p p w m u h , p w m u l , p w m v h , p w m v h , p w m w h , p w m w l t d i t r i p = t i t r i p + g a t e k i l l _ c o n s t _ 1 * 1 0 n s
irmck099m 20 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 6.7 i 2 c ac t iming figure 10 . i 2 c timing unless specified, ta = 25?c. symbol parameter min typ max unit t i2clk i 2 c clock period 10 - - sysclk t i2st1 i 2 c sda start time 0.25 - - t i2clk t i2st 2 i 2 c scl start time 0.25 - - t i2clk t i2wsetup i 2 c write setup time 0.25 - - t i2clk t i2whold i 2 c write hold time 0.25 - - t i2clk t i2rsetup i 2 c read setup time i 2 c filter time (1) - - sysclk t i2rhold i 2 c read hold time 1 - - sysclk table 15 . i 2 c ac timing note: (1) i 2 c read setup time is determined by the programmable filter time applied to i 2 c communication. s c l s d a t i 2 s t 1 t i 2 s t 2 t i 2 w s e t u p t i 2 c l k t i 2 w h o l d t i 2 r s e t u p t i 2 r h o l d t i 2 c l k t i 2 e n 1 t i 2 e n 2
irmck099m 21 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 6.8 uart ac t iming figure 11 . uart timing unless specified, ta = 2 5?c. symbol parameter min typ max unit t baud baud rate period - 57600 - bit/sec t uartfil uart sampling filter period (1) - 1/16 - t baud table 16 . uart ac timing note: (1) each bit including start and stop bit is sampled three t imes at center of a bit at an interval of 1/16 t baud . if three sampled values do not agree, then uart noise error is generated. t x d r x d d a t a a n d p a r i t y b i t s t a r t b i t t b a u d s t o p b i t t u a r t f i l
irmck099m 22 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 6.9 capture i nput ac t iming figure 12 . capture timing unless specified, ta = 25?c. symbol parameter min typ max unit t capclk capture input period 8 - - sysclk t caphigh capture input high time 4 - - sysclk t caplow capture input low time 4 - - sysclk t crdelay capture falling edge to capture register la tch time - - 4 sysclk t cldelay capture rising edge to capture register latch time - - 4 sysclk t intdelay capture input interrupt latency time - - 4 sysclk table 17 . capture ac timing p 1 . 4 / c a p c r e v ( h , l ) i n t e r n a l r e g i s t e r t c a p h i g h t c a p c l k t c r d e l a y t c a p l o w t c l d e l a y c l a s t ( h , l ) i n t e r n a l r e g i s t e r t i n t d e l a y i n t e r r u p t v e c t o r f e t c h i n t e r r u p t
irmck099m 23 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 6.10 jtag ac t iming figure 13 . jtag timing unless specified, ta = 25?c. symbol parameter min typ max unit f jclk tck frequency - - 1 0 mhz t jhigh tck high period 10 - - nsec t jlow tck low period 10 - - nsec t co tck to tdo propagation delay time 0 - 5 nsec t jsetup tdi/tms setup time 4 - - nsec t jhold tdi/tms hold time 0 - - nsec table 18 . jtag ac timing t c k t d o t j h i g h 1 / f j c l k t c o t j l o w t j s e t u p t j h o l d t d i / t m s
irmck099m 24 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 7 i/o structure the following figure shows the i/o structure for all digital pins. at power up, the pr ogrammable pull up transistor is off. figure 14 . d igital i/o structure the following figure shows the analog input /output structure , except for ain0/stby . figure 15 . analog i/o structure the following figure shows all the input structure for ain0/stby pin . figure 16 analog analog input structure for ain0/stby d i g i t a l i / o v d d 1 ( 3 . 3 v ) 4 9 k ? p i n v s s 2 0 0 ? a n a l o g i / o p i n a v s s a n a l o g c i r c u i t v d d c a p ( 1 . 8 v ) 2 0 0 ? a i n 0 / s t b y p i n a v s s a n a l o g c i r c u i t
irmck099m 25 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 the following figure sho ws the vss pin i/o structure figure 17 . vss pin i/o structure the following figure shows the,vddcap pin i/o structure figure 18 . vddcap pin i/o structure the following figure shows the, vdd1 pin i/o structure figure 19 . vdd1 pin i/o structure p i n v d d 1 p i n v s s
irmck099m 26 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 8 pin list pin number pin name internal pull - u p pin type description 1 tdi/ gpio14/gpio15 49 k? pull up (1) i jtag test data input or discrete programmable i/o 2 tck 49 k? pull up (1) i jtag test clock 3 tms/ gpio14 49 k? pull up (1) i/o jtag test mode input or discrete programmable i/o 4 ain3 i analog input channel 3, 0 - 1.2 v range, needs to be p ulled down to vss if unused 5 ain2 i analog input channel 2, 0 - 1.2 v range, needs to be pulled down to vss if unused 6 ain1/vbus i analog input channel 1, 0 - 1.2 v range, used for dc bus voltage input 7 ain0/stby i analog input channel 0, 0 - 1.2 v rang e, exit standby if >300mv 8 ifb2o o operational amplifier output for 2 nd leg shunt resistor current sensing 9 ifb2 - i operational amplifier negative input for 2 nd leg shunt resistor current sensing 10 ifb2+ i operational amplifier positive input for 2 nd leg shunt resistor current sensing 11 ifb1o o operational amplifier output for single or leg shunt resistor current sensing 12 ifb1 - i operational amplifier negative input for single or leg shunt resistor current sensing 13 ifb1+ i operational amplifier positive input for single or leg shunt resistor current sensing 14 vddcap p internal 1.8v output, capacitor(s) to be connected 15 vdd1 p 3.3v digital and analog power 16 vpp p otp programming voltage (6.75v) 17 vss p digital common 18 g pio8 49 k? pull up (1) i/o discrete programmable i/o 19 gpio9 49 k? pull up (1) i/o discrete programmable i/o 20 gpio10 49 k? pull up (1) i/o discrete programmable i/o 21 gpio11 49 k? pull up (1) i/o discrete programmable i/o 22 gpio12 49 k? pull up (1) i/o discrete programmable i/o 23 gpio13 49 k? pull up (1) i/o discrete programmable i/o 24 gpio0 49 k? pull up (1) i /o discrete programmable i/o 25 gpio1 49 k? pull up (1) i/o discrete programmable i/o 26 gpio2 49 k? pull up (1) i/o discrete programmable i/o 27 gpio3 49 k? pull up (1) i/o discrete programmable i/o 28 gpio4 49 k? pull up (1) i/o discrete programmable i/o 29 gpio5 49 k? pull up (1) i/o discrete programmable i/o 30 gpio6 49 k? pull up (1) i/o discrete programmable i/o 31 gpio7 49 k? pull up ( 1) i/o discrete programmable i/o 32 tdo/ gpio14/gpio15 49 k? pull up (1) o jtag test data output or discrete programmable i/o table 19 . pin list (1) programmable internal pull up
irmck099m 27 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 9 package d imensions
irmck099m 28 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 10 part marking information 11 qualification information qu ali f ica t i o n l e v el ?? industrial (per jedec jesd47) m o is tu r e se n si t i v i t y l e v el m s l 2 ??? ( per i p c/ j e d e c j - s t d - 020) esd m ac h i n e m od el c l a s s b ( per j e d e c s ta n da r d j es d22 - a 115) h um an b o d y m od el c l a s s 2 ( per ansi/esda/ j e d e c j s - 001 ) charged device m od el class c2 ( per j e d e c s ta n da r d j es d22 - c101 ) latch - up class i, level b (per j e d e c s ta n da r d j es d78) r o hs c o m p l i a n t y es ? qualification standards can be found at international rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales representative for further information. ??? higher msl ratings may be avail able for the specific package types listed here. please contact your international rectifier sales representative for further information.
irmck099m 29 www.irf.com ? 20 14 international rectifier d ecember 18, 2014 revision history data and specifications are subject to change without notice ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information

▲Up To Search▲

Price & Availability of IRMCK099M-15

	To Download IRMCK099M-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .